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Background

Dr. Vikram Iyengar’s practice* focuses on strategic patent counseling and the preparation and prosecution of U.S. and international patent applications for clients in autonomous vehicles, unmanned aerial vehicles, optics devices, machine learning, server architectures, cloud computing, Internet security, virtual reality devices, satellite technology, networking technology, integrated circuit design, semiconductor manufacturing and social media technology.  Vikram also conducts patent portfolio analysis and intellectual property due diligence for clients in the life sciences and high technology industries.  He combines a deep scientific and technical background with thorough legal analysis to counsel clients in intellectual property matters presenting novel legal challenges that frequently arise from cutting-edge emerging technologies.

As part of his practice, Vikram provides support on inter partes reviews and a broad variety of litigation matters to support clients in the high technology and life sciences industries. His experience includes drafting invalidity claim charts, conducting prior art searches, and working with expert witnesses for patent litigation matters involving computer manufacturers and software corporations.

Prior to joining Fish, Vikram was a Senior Engineer at IBM, where he served on IBM’s Patent Review Board, supported licensing efforts, and was a technical contributor to IBM’s microelectronics business. He designed computer system components for the Watson supercomputer, smartphones, and Internet routers, and is a named inventor on 25 U.S. patents.

Vikram’s graduate work in Electrical & Computer Engineering at Duke University was related to Plug-and-Play Design of computer systems.

*Not admitted to practice in Texas – practice in Texas limited to federal courts and agencies listed below or otherwise authorized by law.

Education

J.D., Stanford Law School 2015
Articles Editor, Stanford Technology Law Review


Ph.D., Duke University 2002
Electrical and Computer Engineering
Outstanding PhD Thesis Award,
European Design Automation Association


M.S., Boston University 1998
Electrical and Computer Engineering


B.E., Birla Institute of Technology 1996
Electrical and Electronics Engineering

Admissions

  • California
  • U.S. Patent and Trademark Office
  • U.S. Court of Appeals for the Ninth Circuit
  • United States District Court for the Central District of California
  • United States District Court for the Northern District of California

Other Distinctions

Publications

The Evolving Standard for Patent Claim Definiteness. Daily J. (2018).

Revisiting NAFTA Could Mean Stronger Protections for IP Owners, Daily J. (2018).

Implications of Certiorari Denial in Belmora v. Bayer Consumer Care, Intellectual Property Law Bulletin (2017).

Patent Derivation at the Federal Circuit, Daily J. (2017).

Offshore Patent Transfer Payments Draw IRS, Court Scrutiny, Law360 (2016).

The Relevance of Expert Testimony to Claims of “Deliberate Indifference” Under the Eighth Amendment, 52 Criminal Law Bulletin 43 (2016).

Should Pharmaceutical Product Hopping Be Subject to Antitrust Scrutiny? 97 J. Patent & Trademark Office Soc. 663 (2015).

Mylan v. Warner Chilcott: A Study in Pharmaceutical Product Hopping, 19 Marquette Intellectual Property Law Review 245 (2015).

U.S. v. Jones: Inadequate to Promote Privacy for Citizens or Efficiency for Law Enforcement, 19 Tex. J. C.L. & C.R. 335 (2014).

Maryland v. King: The Case for Uniform, Nation-Wide DNA Collection and DNA Database Laws, 23 Information & Communication Technology Law Journal Online 77 (2014).

Physically-aware N-detect test, with Y.-T. Lin, O. Poku, R. D. Blanton, P. Nigh and P. Lloyd. IEEE Transactions on Computer-Aided Design, vol. 31, pp. 308–321, February 2012.

Wafer-level defect screening for ‘big-D/small-A’ mixed-signal system chips, with S. Bahukudumbi, S. Ozev, and K. Chakrabarty. IEEE Transactions on VLSI Systems, pp. 587-592, April 2009.

Design Verification, in The VLSI Handbook, 2nd edition, W-K. Chen (Ed.). CRC Press, Boca Raton, FL and IEEE Press, New York, NY, 2006.

Test Resource Partitioning for System-on-a-Chip, with K. Chakrabarty and A. Chandra. Kluwer Academic Publishers, Norwell, MA, 2002.